1. Field of the Invention
The present invention relates to a method and apparatus for providing an improved dielectric property between adjacent conductive lines in a semiconductor device. More particularly, the present invention relates to a method and apparatus where the space between closely proximate conductive lines comprises an air void, e.g. a space not filled by either: (i) the dielectric material usually needed for insulation between layers of conductive lines; or 2) the passivation overcoat formed on the top layer of conductive lines. As a result, the invention provides for minimum capacitive coupling because the space between closely positioned conductive lines is free space having a unitary dielectric constant.
2. Description of the Related Art
The integrated circuit industry is constantly reducing the separation between conductive lines to achieve a smaller integrated circuit. Minimizing integrated circuit area is important because it yields many benefits including higher reliability, lower cost, and higher speed.
Reducing the spacing between the conductive lines in an integrated circuit, however, results in an increase in the amount of capacitive crosstalk between these conductive lines. In conventional integrated circuits, the interconnect arrangement typically consists of many adjacent conductive lines. If the capacitive crosstalk between a first conductive line and a second conductive line is high, then the voltage on the first conductive line alters or affects the voltage on the second line. This alteration in voltage could cause an integrated circuit to misinterpret logic levels and/or voltage levels and, therefore, incorrectly process binary and/or analog information. An integrated circuit that incorrectly processes any information is usually considered inoperable or faulty.
Illustrated in FIG. 1 is a semiconductor structure having two conductive lines. FIG. 1 depicts a conductive line 1 and a conductive line 2 adjacent to conductive line 1. Each of conductive lines 1 and 2 has a width "w," and conductive line 1 is separated from conductive line 2 by a separation distance "s." A quantity known as a pitch (pitch=w+s) is conventionally used to characterize capacitive crosstalk for adjacent conductive lines used in the integrated circuit industry.
As noted above, a reduction of pitch is an ongoing activity in the integrated circuit industry to achieve integrated circuits which are more dense and use substrate surface area more efficiently. The capacitance between conductive lines 1 and 2 has been found to increase exponentially as pitch is reduced or as the conductive lines 1 and 2 are brought closer together.
This increase in capacitive coupling between conductive lines 1 and 2 is a disadvantage because of the resulting increase in the amount of capacitive crosstalk between the conductive lines. For instance, if conductive line 1 is separated from conductive line 2 by one hundred microns, the coupling capacitance will be small and there will be virtually no capacitive crosstalk between the conductive lines. If the pitch is less than approximately one micron, however, the capacitive coupling between the conductive lines will be high. Consequently, the amount of capacitive crosstalk will be high and may render the particular integrated circuit inoperable.
Capacitive crosstalk is a phenomenon wherein a voltage level at conductive line 1 adversely effects and/or alters the voltage level at conductive line 2 through the capacitive coupling between conductive lines 1 and 2. Assume that the pitch in a conductive layer of a DRAM is 2 microns and that the DRAM has a plurality of data lines and address lines. These address and data lines are typically run across the integrated circuit together or in groups. The conductive lines making up these data lines and address lines are separated by a minimum pitch to conserve surface area on the integrated circuit. One data or address line may be carrying a logic one (i.e., a five volt signal). An adjacent data or address line may be carrying a logic zero (i.e., a zero volt signal or ground potential).
The capacitive crosstalk due to this small pitch may cause the logic one value on the first line to effect and/or alter the logic zero value on the adjacent line and/or vice versa. Therefore, instead of properly carrying the correct logic one voltage level or logic zero voltage level, the address and data lines may carry an erroneous voltage level. This erroneous voltage level could alter the operation of the DRAM rendering it faulty or inoperable. Crosstalk phenomenon may have an even greater effect on the operation of analog circuitry.
One prior art method for reducing capacitive coupling, and therefore for reducing capacitive crosstalk between conductive lines having a small pitch, is the use of low dielectric constant materials to replace the conventional dielectric materials which are typically used for insulation between conductive layers and the passivation overcoat layer formed on the top conductive layer. Conventional semiconductor dielectric materials have a dielectric constant of about four. Some new dielectric materials, such as Teflon may have a dielectric constant between about two and four. The use of many dielectric materials having low dielectric constants, however, is not feasible because the equipment necessary to process properly the new dielectric materials in integrated circuits is not available. Also, the chemical or physical properties of many of these dielectric materials may be difficult to integrate into conventional integrated circuit processing.
Another prior art method for reducing capacitive crosstalk between conductive lines having a small pitch is the use of coaxial cable type arrangements in integrated circuits. A coaxial arrangement typically consists of a first conductor which carries a signal and a second conductor surrounding the first conductor which is used to shield the first conductor from other conductors in the integrated circuit. This coaxial arrangement is very difficult to form in a integrated circuit since one conductor must be entirely surrounded by a second conductor. Furthermore, this coaxial arrangement requires two or more conductive layers. Thus, one functional layer of conductive interconnect requires several layers of conductive material. The use of several conductive layers to form one functional conductive interconnect layer is simply not a cost effective method for reducing capacitive crosstalk between conducive lines with a small pitch.
Another prior art method for reducing capacitive crosstalk between conductive lines having a small pitch proposes a partial air gap in the dielectric region between these conductive lines. In this method, a plug is formed between adjacent conductive lines to provide a partial air gap between these conductive lines when the interlevel insulation or passivation overcoat is formed on top of this plug. This method, however, does not provide a material free region between these conductive lines (i.e. 100% air gap) and will not achieve a dielectric constant approaching 1. Furthermore, this method entails the use of many additional complex and costly processing steps to form the plug and thus is not a simple and cost effective method for reducing capacitive crosstalk.
For example, if a dielectric layer having a dielectric constant of 4.3 is used as an interlevel dielectric, then, if there is no air gap (percentage of air gap=0%), the entire region between the conductive lines depends solely upon the dielectric constant of the dielectric material used; 4.3 in this example. If a 50% air gap is formed between conductors, i.e. only 50% of the region between the conductive lines is dielectric material, the effective dielectric constant of the region between the conductive regions is reduced to K =2.75 and, thus, the capacitance is reduced. The dielectric value K=2.75 is 50% due to air and 50% due to the remaining dielectric regions. Ideally, a material free region (100% air gap) is desired wherein the capacitance is very low and the dielectric constant is reduced significantly.
Yet another prior art method for reducing capacitive crosstalk between conductive lines with a small pitch proposes a material free region (100% air gap) between these conductive lines. In this method three layers including a growth or seed layer in the middle must be formed on top of the conductive lines. Then the sidewall of the growth or seed layer is selectively grown to close off the opening between the conductive lines to form the material free region. This method also entails the use of many additional, complex, and costly processing steps and, therefore, is not a simple and cost effective method for reducing capacitive crosstalk.
Thus, to maintain a small pitch between conductive lines on an integrated circuit and therefore achieve a denser, lower costing integrated circuit, a new, simpler and more cost effective method for reducing coupling capacitance, and therefore reducing capacitive crosstalk between these conductive lines, is needed.